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? semiconductor components industries, llc, 2002 june, 2002 rev. 1 1 publication order number: and8016/d and8016/d design of power factor correction circuit using greenline ? compact power factor controller mc33260 prepared by ming hian chew on semiconductor analog applications engineering introduction the mc33260 is an active power factor controller that functions as a boost preconverter which, meeting international standard requirement in electronic ballast and offline power supply application. mc33260 is designed to drive a free running frequency discontinuous mode, it can also be synchronized and in any case, it features very effective protections that ensure a safe and reliable operation. this circuit is also optimized to offer extremely compact and cost effective pfc solutions. it does not entail the need of auxiliary winding for zero current detection hence a simple coil can be used instead of a transformer if the mc33260 vcc is drawn from the load (please refer to page 19 of the data sheet). while it requires a minimum number of external components, the mc33260 can control the follower boost operation that is an innovative mode allowing a drastic size reduction of both the inductor and the power switch. ultimately, the solution system cost is significantly lowered. also able to function in a traditional way (constant output voltage regulation level), any intermediary solutions can be easily implemented. this flexibility makes it ideal to optimally cope with a wide range of applications. this application note will discuss on the design of power factor correction circuit with mc33260 with traditional boost constant output voltage regulation level operation and follower boost variable output voltage regulation level operation. for derivation of the design equations related to the ic please refer to mc33260 data sheet. figure 1. application schematic of mc33260 1 2 3 4 8 7 6 5 mc33260 c5 + d5 q1 r5 r4 r3 r2 c1 d1 d3 d2 d4 + c4 r6 d5 d7 r7 r1 c2 c3 l1 c6 pfc techniques many pfc techniques have been proposed, boost topology, which can operate in continuous and discontinuous mode, is the most popular. typically, continuous mode is more favorable for high power application for having lower peak current. on the other hand, for less than 500 w application, discontinuous mode offers smaller inductor size, minimal parts count and lowest cost. this paper will discuss design of pfc with mc33260, which operates in critical conduction mode. discontinuous conduction mode operation critical conduction mode operation presents two major advantages in pfc application. for critical conduction mode, the inductor current must fall to zero before start the next cycle. this operation results in higher efficiency and application note http://onsemi.com
and8016/d http://onsemi.com 2 eliminates boost rectifier reverse recovery loss as mosfet cannot turnon until the inductor current reaches zero. secondly, since there are no deadtime gaps between cycles, the ac line current is continuous thus limiting the peak switch to twice the average input current. the converter works right on critical conduction mode, which results in variable frequency operation. inductor waveform v l di dt (1 ) equation (1) is the center of the operation of pfc boost converter where v=v in (t), the instantaneous voltage across the inductor. assuming the inductance and the ontime over each line halfcycle are constant, di is actually the peak current, i lpk , this is because the inductor always begins charging at zero current. figure 2. inductor waveform v inpk i lpk i inpk v in (t) i l (t) i in (t) on off mosfet design criteria the basic design specification concerns the following: ? mains voltage range: v ac(ll) v ac(hl) ? regulated dc output voltage: v o ? rated output power: p o ? expected efficiency, pfc power section design instantaneous input voltage, v in (t) peak input voltage, v inpk both v in (t) and v inpk are related by below equation v in (t) v inpk sin( w t) (2) v inpk 2
v inrms (3) where instantaneous input current, i in (t) peak input current, i inpk , both i in (t) and i inpk are related by below equation i in (t) i inpk sin( w t), (4) i inpk 2
i inrms (5) where input power of the pfc circuit, p in can be expressed in following equation, by substituting equation (3) and (5). p in v inrms i inrms v inpk 2
i inpk 2
v inpk i inpk 2 (6 ) the output power, p o is given by: p o v o i o h p in (7) pfc circuit efficiency is needed in the design equation, for low line operation, it is typically set at 92% while 95% for high line operation. substituting equation (6) into equation (7), p o h p in h v inpk i inpk 2 (8) express the above equation in term of i inpk , i inpk 2p o h v inpk 2
p o h v inrms (9) the average input current is equal to average inductor current, i l(avg) , i l(avg) i in (10) it has been understood that peak inductor current, i lpk is exactly twice the average inductor current, i l(avg) for critical conduction operation. i lpk 2i l(avg) 22
p o h v inrms (11) since i lpk is maximum at minimum required ac line voltage, v ac(ll) , i lpk 22
p o h v ac(ll) (12) switching time in theory, the ontime, t (on) is constant. in practice, t (on) tends to increase at the ac line zero crossings due to the charge on output capacitor c out . let v ac = v ac(ll) for initial t (on) and t (off) calculations. ontime by solving inductor equation (1), ontime required to charge the inductor to the correct peak current is: t (on) i lpk l p vinpk (13) substituting equation (3) and (12) into equation (13), results in: t (on) 22
p o h v ac(ll) l p 2
v ac(ll) 2p o l p h v 2 ac(ll) (14)
and8016/d http://onsemi.com 3 offtime the instantaneous switch offtime varies with the line and load conditions, as well as with the instantaneous line voltage. of ftime is analyzed by solving equation (1) for the inductor discharging where the voltage across the inductor is v o minus v in . t (off) i lpk l p v o v inpk sin( w t) (15) multiplying nominator and denominator with v inpk sin (t) results in: t (off) (16) i lpk l p v inpk sin( w t) v o v inpk sin( w t) v inpk sin( w t) v o 2
vinpk sin( q ) 1 t (on) where t = the offtime, t (off) is greatest at the peak of the ac line voltage and approaches zero at the ac line zero crossings. theta ( ) represents the angle of the ac line voltage. the offtime is at a minimum at ac line crossings. this equation is used to calculate t (off) as theta approaches zero. t (off)min i lpk l p v o , q 0 (17) switching frequency f 1 t ( on ) t ( off ) (18) switching frequency changes with the steady state line and load operating conditions along with the instantaneous input line voltage. typically, the pfc converter is designed to operate above the audible range after accommodating all circuit and component tolerances. 25 khz is a good first approximation. higher frequency operation that can significantly reduce the inductor size without negatively impacting efficiency or cost should also be evaluated. the minimum switching frequency occurs at the peak of the ac line voltage. as the ac line voltage traverses from peak to zero, t (off) approaches zero producing an increase in switching frequency. inductor value maximum ontime needs to be programmed into the pfc controller timing circuit. both t (on)max and t (off)max will be individually calculated and added together to obtain the maximum conversion period, t total . this is required to obtain the inductor value. t (on)max 2p o l p h v 2 ac(ll) (19) t (off)max i lpk l p v o v inpk ,( q ) 90 (20) the exact inductor value can be determined by solving equation (21) by substituting equation (19) and (20) at the selected minimum operating frequency. t total t (on)max t (off)max (21) equation (21) becomes t total 2
p o l p v o v 2 ac(ll) h v o 2
v ac(ll) (22) by rearranging in term of l p , l p t total v o 2
v ac(ll) h v 2 ac(ll) 2
v o p o (23) equation (23) can be rewritten by substituting rearranged equation (12) in term of 2p o . l p 2 t total v o 2
v ac(ll) v ac(ll) v o i lpk (24) let the switching cycle t = 40 s for universal input (85 to 265 v ac ) operation and 20 s for fixed input (92 to 138 v ac , or 184 to 276 v ac ) operation. inductor design summary the required energy storage of the boost inductor is: w l 1 2 l p i 2 lpk (25) the number of turns required for a selected core size and material is: n p l p i lpk 10 6 b max a e (26) where b max is in teslas and a e is in square millimeters (mm 2 ) the required air gap to achieve the correct inductance and storage is expressed by: l gap 4 10 7 n 2 p a e l p mm (27) design of auxiliary winding mc33260 does not entail an auxiliary winding for zero current detection. hence if dc voltage can be tapped from the smps or electronic ballast connected to the output of pfc, this step can be skipped. then an inductor is what it needs. the auxiliary winding exhibits a low frequency ripple (100120 hz). the vcc capacitor must be large enough (about 47 f) to minimize voltage variations. as a rule of thumb, you can use the below equation to estimate the auxiliary turn number: (28) n aux n p v aux v l n p v aux v o v ac(hl)
and8016/d http://onsemi.com 4 the mc33260 v cc maximum voltage being 16 v, one must add a resistor (in the range of 22 ) and a 15 v zener to protect the circuit against excessive voltages. vaux should be chosen above the undervoltage lockout threshold (10 v) and below the zener voltage. selection of output capacitor the choice of output capacitance value is dictated by the required holdup time, t hold or the acceptable output ripple voltage, v orip for a given application. as a rule of thumb, can start with 1 f/watt. selection of semiconductors maximum currents and voltages must first be determined for over all operating conditions to select the mosfet and boost rectifier. as a rule of thumb, derate all semiconductors to about 7580% of their maximum ratings. this implying the need of devices with at least 500 v breakdown voltage. bipolar transistors are an acceptable alternative to mosfet if the switching frequency is maintained fairly low. high voltage diodes with recovery times of 200 ns, or less should be used for the boost rectifier. one series of the popular devices is the murxxx ultrafast rectifier series from on semiconductor. maximum power mosfet conduction losses. p (on)max 1 6 r ds(on) i 2 lpk 1 1.2 v ac(ll) v o (29) designing the oscillator circuit for traditional boost operation, c t is chosen with below equation: c t 2 k osc l p p in v 2 o v 2 ac ( ll ) r 2 o c int (30) design of regulation and overvoltage protection circuit the output voltage regulation level can be adjusted by r o , r o v o 200 a (31) designing the current sense circuit the inductor current is converted into a voltage by inserting a ground referenced resistor, r cs in series with the input diode bridge. therefore a negative voltage proportional to the inductor current is built. the current sense resistor losses, p rcs : p rcs 1 6 r cs i 2 lpk (32) overcurrent protection resistor, r ocp can be determined with below equation: r ocp r cs i lpk i oc p (33) current limiting with boost topology power factor correction circuit unlike buck and flyback circuits, because there is no series switch between input and output in the boost topology, high current occurring with the startup inrush current surge charging the bulk capacitor and fault load conditions cannot be limited or controlled without additional circuitry. the mc33260 zero current detection uses the current sensing information to prevent any power switch turn on as long as some current flows through the inductor. then, during startup, the power mosfet is not allowed to turn on while inrush current flows. then there is no risk to have the power switch destroyed at startup because of the inrush current. in the same way, in an overload case, the power mosfet is kept off as long as there is a direct output capacitor charge current, i.e., when the input voltage is higher than the output voltage. consequently, overload working is fully safe for the power mosfet. this is one of the major advantages compared to mc33262 and competition. current limiting for startup inrush initially v o is zero, when the converter is turned on, the bulk capacitor will charge resonantly to twice vin. the voltage can be as high as 750 v if v in happens to be at the peak highline 265 v condition (375 v). the peak resonant charging current through the inductor will be many times greater than normal full load current. the inductor must be designed to be much larger and more expensive to avoid saturation. the boost shunt switch cannot do anything to prevent this and could be worse if turned on during startup. the inrush current and voltage overshoot during the startup phase is intolerable. a fuse is not suitable, as it will blow each time the supply is turned on. there are several methods that may be used to solve the startup problem: 1. startup bypass rectifier this is implemented by adding an additional rectifier bypassing the boost inductor. the bypass rectifier will divert the startup inrush current away from the boost inductor as shown in figure 3. the bulk capacitor charges through d bypass to the peak ac line voltage without resonant overshoot and with out excessive inductor current. d bypass is
and8016/d http://onsemi.com 5 reversebiased under normal operating conditions. if load overcurrent pulls down v o , d bypass conducts, but this is probably preferable to having the high current flowing through boost inductor. figure 3. rectifier bypass of startup inrush current v ac v out d bypass + pfc ic 2. external inrush current limiting circuit for low power system, a thermistor in series with the preconverter input will limit the inrush current. concern is the thermistor may not respond fast enough to provide protection after a line dropout of a few cycles. a series input resistor shunted by a triac or scr is a more efficient approach. a control circuit is necessary. this method can function on a cyclebycycle basis for protection after a dropout. load overcurrent limiting if an overcurrent condition occurs and exceeds the boost converter power limit established by the control circuit, v o will eventually be dragged down below the peak value of the ac line voltage. if this happens, current will rise rapidly and without limit through the series inductor and rectifier. this may result in saturation of the inductor and components will fail. the control circuit holds off the shunt switch, since the current limit function is activated. it cannot help to turn the switch on the inductor current will rise even more rapidly and switch failure will occur. typically, a power factor correction circuit is connected to another systems like switched mode power supply or electronic ballast. these downstream converters typically will have current limiting capability, eliminating concern about load faults. however, a downstream converter or the bulk capacitor might fail. hence there is a possibility of a short circuit at the load. if it is considered necessary to limit the current to a safe value in the event of a downstream fault, some means external to the boost converter must be provided. design example i traditional boost constant output voltage regulation level operation power factor correction the basic design specification concerns the following: ? mains voltage range: v ac(ll) v ac(hl) = 85 265 v ac ? regulated dc output voltage: v o = 400 v dc ? rated output power: p o = 80 w ? expected efficiency, > 90% a. the input power, pin is given by p in p o h 80 0.92 86.96 w b. input diode current is maximum at v inrms = v ac(ll) i inpk 2
p o h v ac(ll) 2
80 0.92 85 1.447 a c. inductor design 1. inductor peak current: i lpk 2i inpk 2 1.447 2.894 a 2. inductor value: l p 2 t total v o 2
v ac(ll) v ac(ll) v o i lpk 2 40 10 6 400 2
85 85 400 2.894 1.162 mh let the switching cycle t = 40 s for universal input (85 to 265 v ac ) operation. 3. the number of turns required for a selected core size and material is: n p l p i lpk 10 6 b max a e 1.162 10 3 2.894 10 6 0.3 60 186.8 turns 187 turns using epcos e 30/15/7, b max =0.3 t and a e = 60 mm 2 . 4. the required air gap to achieve the correct inductance and storage is: l gap 4 10 7 n 2 p a e l p 4 10 7 187 2 60 10 6 1.162 10 3 2.269 mm 5. design of auxiliary winding n aux v aux n p v o v ac(hl) 14 187 (400 265) 19.4 turns 20 turns round up to 20 turns to make sure enough voltage at the auxiliary winding.
and8016/d http://onsemi.com 6 d. to determine the output capacitor as rule of thumb, for 80 w output, start with 100 f, 450 v capacitor. e. calculation of mosfet conduction losses a 8a, 500v mosfet, mtp8n50e is chosen. the on resistance, r ds(on) 1.75 @100 c. therefore, maximum power mosfet conduction losses is: p (on)max 1 6 r ds(on) i 2 lpk 1 1.2 v ac(ll) v o 1 6 1.75 2.894 2 1 1.2 85 400 1.82 w f. design of regulation and overvoltage protection circuit the output voltage regulation level can be adjusted by r o , r o v o 200 m a 400 200 m a 2m w use two 1 m resistors in series. g. designing the oscillator circuit for traditional boost operation, c t is chosen with below equation: c t 2 k osc l p p in v 2 o v 2 ac(ll) r 2 o c int 2 6400 1.162mh 86.96 400 2 85 2 2m w 2 15pf 7.16nf use 10 nf capacitor. figure 4. theoretical v o versus v ac with c t = 10nf vo/(v) 85 115 175 85 145 v ac (v) 145 175 115 445 205 235 205 235 265 295 325 355 385 415 265 100 1130 190 160 220 250 28 0 full load half load vacpeak h. design of the current sense circuit choose r cs = 0.68 1. so the current sense resistor losses, p rcs : p rcs 1 6 r cs i 2 lpk 1 6 1 2.894 2 0.949 w therefore the power rating of r cs is chosen to be 2 w. 2. overcurrent protection resistor, r ocp can be determined with below equation: r ocp r cs i lpk i ocp 0.68 2.894 205 m a 9600 w use 10000 resistor. this provide current limit at 3.01 a versus calculated value of i lpk = 2.894 a. 80 w, universal input, traditional boost constant output voltage level regulation operation power factor correction circuit part list index value comment index value comment c1 0.63 f@600 v filtering capacitor r6 22 @0.25 w aux winding resistor c2 680 nf pin 2 v control capacitor r7 100 k @2 w startup resistor c3 10 nf pin 3 oscillator capacitor r8 1n5406 input diode c4 100 f@50 v aux capacitor, ecap d1 1n5406 input diode c5 100 f@450v output capacitor, ecap d2 1n5406 input diode c6 1 nf@50 v feedback filtering capacitor d3 1n5406 input diode r1 0.68 @2 w current sense resistor d4 1n4937 aux winding diode r2 10 k @0.25 w ocp sensing resistor d5 mur460 boost diode r3 1 m @0.25 w feedback resistor d6 1n5245 aux 15 v zener diode r4 1 m @0.25 w feedback resistor d7 mtp8n50e power mosfet r5 10 @0.25 w gate resistor q1 1.162 mh inductor * e 30/15/7, n67 material from epcos primary 187 turns of # 23 awg, secondary 19 turns of # 23 awg. gap length 2.269mm total for a primary inductance l p of 1.162mh.
and8016/d http://onsemi.com 7 figure 5. 80 w universal input, traditional boost constant output voltage regulation level operation power factor correction circuit 1 2 3 4 8 7 6 5 mc33260 c5 + d5 q1 r5 r4 r3 r2 c1 d1 d3 d2 d4 + c4 r6 d5 d7 r7 r1 c2 c3 l1 c6 design table for universal input, traditional boost constant output voltage regulation level operation power factor correction p o 25 50 75 100 125 150 200 (watts) l p 3.720 1.860 1.240 0.930 0.744 0.620 0.465 (mh) c o 33 68 100 100 150 150 220 ( f) r cs 2 1 0.68 0.5 0.39 0.33 0.25 r ocp 10000 10000 10000 9100 9100 9100 9100 c in 0.22 0.63 0.63 1.0 1.0 1.0 1.0 ( f) c t 10 10 10 10 10 10 10 (nf) q mtp4n50e mtp8n50e mtw14n50e d out mur160 mur460 d in 1n4007 1n5406 design example ii follower boost variable output voltage regulation level operation power factor correction the basic design specification concerns the following: ? mains voltage range: v ac(ll) v ac(hl) = 85 265 v ac ? maximum regulated dc output voltage: v o = 400 v dc ? minimum regulated dc output voltage: v omin = 140 v dc ? rated output power: p o = 80 w ? expected efficiency, > 90% a. the input power, p in is given by p in p o h 80 0.92 86.96 w b. input diode current is maximum at v inrms = v ac(ll) i inpk 2
p o h v ac(ll) 2
80 0.92 85 1.447 a c. inductor design 1. inductor peak current: i lpk 2i inpk 2 1.447 2.894 a 2. inductor value, for follower boost operation, v o = v omin :
and8016/d http://onsemi.com 8 l p 2 t total v omin 2
v ac(ll) v omin i lpk 2 40 10 6 140 2
85 85 140 2.894 0.235 m h let the switching cycle t = 40 s for universal input (85 to 265 v ac ) operation. 3. the number of turns required for a selected core size and material is: n p l p i lpk 10 6 b max a e 0.235 10 3 2.894 10 6 0.3 32.1 70.6 turns 71 turns using epcos e 20/10/6, n67 material, b max =0.3 t and a e = 32.1 mm 2 . 4. the required air gap to achieve the correct inductance and storage is: l gap 4 10 7 n 2 p a e l p 4 10 7 71 2 32.1 10 6 0.235 10 3 0.856 mm 5. design of auxiliary winding n aux v aux n p v o v ac(hl) 14 71 (400 265) 7.4 turns 8 turns round up to 8 turns to make sure enough voltage at the auxiliary winding. d. to determine the output capacitor as rule of thumb, for 80 w output, start with 100 f, 450 v capacitor. e. calculation of mosfet conduction losses a 4a, 500 v mosfet, mtp4n50e is chosen. the on resistance, r ds(on) 1.75 @100 c. therefore, maximum power mosfet conduction losses is: p (on)max 1 6 r ds(on) i 2 lpk 1 1.2 v ac(ll) v omin 1 6 1.75 2.894 2 1 1.2 85 140 0.66 w f. design of regulation and overvoltage protection circuit the output voltage regulation level can be adjusted by r o , r o v o 200 m a 400 200 m a 2m w use two 1m resistors in series. g. designing the oscillator circuit for follower boost operation, c t is chosen with below equation: c t 2 k osc l p p in v 2 o v 2 ac(ll) r 2 o c int 2 6400 0.234mh 86.96 140 2 85 2 2m w 2 15pf 162 pf use 150 pf capacitor. figure 6. theoretical v o versus v ac with c t = 150pf vo/(v) 85 115 175 85 145 v ac (v) 145 175 115 445 205 235 205 235 265 295 325 355 385 415 265 100 1130 190 160 220 250 28 0 full load half load vacpeak h. design of the current sense circuit choose r cs = 0.68 1. so the current sense resistor losses, p rcs : p rcs 1 6 r cs i 2 lpk 1 6 0.68 2.894 2 0.949 w 2. overcurrent protection resistor, r ocp can be determined with below equation: r ocp r cs i lpk i ocp 0.68 2.894 205 m a 9600 w use 10000 resistor. this provide current limit at 3.01 a versus calculated value of i lpk = 2.894 a.
and8016/d http://onsemi.com 9 80 w, universal input, follower boost variable output voltage regulation level operation power factor correction circuit part list index value comment index value comment c1 0.63 f@600 v filtering capacitor r6 22 @0.25 w aux winding resistor c2 680 nf pin 2 v control capacitor r7 100 k @2 w startup resistor c3 150 pf pin 3 oscillator capacitor d1 1n5406 input diode c4 100 f@50 v aux capacitor, ecap d2 1n5406 input diode c5 100 f@450 v output capacitor, ecap d3 1n5406 input diode c6 1 nf@50 v feedback filtering capacitor d4 1n5406 input diode r1 0.68 @2 w current sense resistor d5 1n4937 aux winding diode r2 10 k @0.25 w ocp sensing resistor d6 mur460 boost diode r3 1 m @0.25 w feedback resistor d7 1n5245 aux 15 v zener diode r4 1 m @0.25 w feedback resistor q1 mtp4n50e power mosfet r5 10 @0.25 w gate resistor l1* 0.235 mh inductor * e 20/10/6, n67 material from epcos primary 71 turns of # 23 awg, secondary 8 turns of # 23 awg. gap length 0.865 mm total for a primary inductance l p of 0.235 mh. figure 7. 80 w universal input, follower boost variable output voltage regulation level operation power factor correction circuit 1 2 3 4 8 7 6 5 mc33260 c5 + d5 q1 r5 r4 r3 r2 c1 d1 d3 d2 d4 + c4 r6 d5 d7 r7 r1 c2 c3 l1 c6
and8016/d http://onsemi.com 10 design table for universal input, follower boost variable output voltage regulation level operation power factor correction p o 25 50 75 100 125 150 200 (watts) l p 0.752 376 0.251 0.188 0.150 0.102 0.094 (mh) c o 33 68 100 100 150 150 220 ( f) r cs 2 1 0.68 0.5 0.39 0.33 0.25 r ocp 10000 10000 10000 9100 9100 9100 9100 c in 0.22 0.63 0.63 1.0 1.0 1.0 1.0 ( f) c t 0.162 0.162 0.162 0.162 0.162 0.162 0.162 (nf) q mtd2n50e mtp4n50e mtp8n50e d out mur160 mur460 d in 1n4007 1n5406 1n5406
and8016/d http://onsemi.com 11 notes
and8016/d http://onsemi.com 12 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. and8016/d greenline is a trademark of semiconductor components industries, llc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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